Datasheet

6.6.5 System Options Register 1 (SYS_SOPT1)
Address: 3000h base + 4h offset = 3004h
Bit 7 6 5 4 3 2 1 0
Read
SCI0PS SPI0PS IICPS FTM2PS BKGDPE RSTPE FWAKE STOPE
Write
Reset
0 0 0 0 1 1 0 0
SYS_SOPT1 field descriptions
Field Description
7
SCI0PS
SCI0 Pin Select
This write-once bit selects the SCI0 pinouts.
0 SCI0 RxD and TxD are mapped on PTB0 and PTB1.
1 SCI0 RxD and TxD are mapped on PTA2 and PTA3.
6
SPI0PS
SPI0 Pin Select
This write-once bit selects the SPI0 Pinouts.
0 SPI0 SPSCK0, MOSI0, MISO0, and SS0 are mapped on PTB2, PTB3, PTB4, and PTB5.
1 SPI0 SPSCK0, MOSI0, MISO0, and SS0 are mapped on PTE0, PTE1, PTE2, and PTE3.
5
IICPS
IIC Port Pin Select
This write-once bit selects the IIC port pins.
0 IIC SCL and SDA are mapped on PTA3 and PTA2, respectively.
1 IIC SCL and SDA are mapped on PTB7 and PTB6, respectively.
4
FTM2PS
FTM2 Port Pin Select
This write-once bit selects the FTM2 channels port pins.
0 FTM2 channels mapped on PTC0, PTC1, PTC2, PTC3, PTB4, and PTB5.
1 FTM2 channels mapped on PTH0, PTH1, PTD0, PTD1, PTB4, and PTB5.
3
BKGDPE
Background Debug Mode Pin Enable
This write-once bit when set enables the PTA4/ACMPO/BKGD/MS pin to function as BKGD/MS. When
clear, the pin functions as output only PTA4. This pin defaults to the BKGD/MS function following any
MCU reset.
0 PTA4/ACMPO/BKGD/MS as PTA4 or ACMPO function.
1 PTA4/ACMPO/BKGD/MS as BKGD function.
2
RSTPE
RESET Pin Enable
This write-once bit can be written after any reset. When RSTPE is set, the PTA5/IRQ/TCLK0/RESET pin
functions as RESET. When clear, the pin functions as one of its alternative functions. This pin defaults to
PTA5 following an MCU POR. Other resets will not affect this bit. When RSTPE is set, an internal pullup
device on RESET is enabled.
0 PTA5/IRQ/TCLK0/RESET pin functions as PTA5, IRQ, or TCLK0.
1 PTA5/IRQ/TCLK0/RESET pin functions as RESET.
Table continues on the next page...
Chapter 6 System control
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 141