Datasheet

SYS_SOPT1 field descriptions (continued)
Field Description
1
FWAKE
Fast Wakeup Enable
This write once bit can set CPU wakeup without any interrupt subroutine serviced. This action saved more
than 11 cycles(whole interrupt subroutine time). After wake up CPU continue the address before wait or
stop.
NOTE: When FWAKE is set, user should avoid generating interrupt 0~8 bus clock cycles after issuing
the stop instruction, or the MCU may stuck at stop3 mode and cannot wake up by interrupts.
0 CPU wakes up as normal.
1 CPU wakes up without any interrupt subroutine serviced.
0
STOPE
Stop Mode Enable
This write-once bit defaults to 0 after reset, which disables stop mode. If stop mode is disabled and a user
program attempts to execute a STOP instruction, an illegal opcode reset occurs.
0 Stop mode disabled.
1 Stop mode enabled.
6.6.6 System Options Register 2 (SYS_SOPT2)
This register may be read/write at any time. SYS_SOPT2 should be written during the
user's reset initialization program to set the desired controls even if the desired settings
are the same as the reset settings.
Address: 3000h base + 5h offset = 3005h
Bit 7 6 5 4 3 2 1 0
Read
TXDME
0
RXDFE RXDCE ACIC RTCC ADHWTS
Write FTMSYNC
Reset
0 0 0 0 0 0 0 0
SYS_SOPT2 field descriptions
Field Description
7
TXDME
SCI0 TxD Modulation Select
This bit enables the SCI0 TxD output modulated by FTM0 channel 0.
0 TxD0 output is connected to pinout directly.
1 TxD0 output is modulated by FTM0 channel 0 before mapped to pinout.
6
FTMSYNC
FTM2 Synchronization Select
Writing a 1 to this bit generates a PWM synchronization trigger to the FTM modules.
0 No synchronization triggered.
1 Generate a PWM synchronization trigger to the FTM2 modules.
Table continues on the next page...
System Control Registers
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
142 Freescale Semiconductor, Inc.