Datasheet

SYS_SOPT2 field descriptions (continued)
Field Description
5
RXDFE
SCI0 RxD Filter Select
This bit enables the SCI0 RxD input filtered by ACMP. When this function is enabled, any signal tagged
with ACMP inputs can be regarded SCI0.
0 RXD0 input signal is connected to SCI0 module directly.
1 RXD0 input signal is filtered by ACMP, then injected to SCI0.
4
RXDCE
SCI0 RxD Capture Select
This bit enables the SCI0 RxD is captured by FTM0 channel 1.
0 RXD0 input signal is connected to SCI0 module only.
1 RXD0 input signal is connected to SCI0 module and FTM0 channel 1.
3
ACIC
Analog Comparator to Input Capture Enable
This bit connects the output of ACMP to FTM1 input channel 0.
0 ACMP output not connected to FTM1 input channel 0.
1 ACMP output connected to FTM1 input channel 0.
2
RTCC
Real-Time Counter Capture
This bit allows the Real-time Counter (RTC) overflow to be captured by FTM1 channel 0.
0 RTC overflow is not connected to FTM1 input channel 1.
1 RTC overflow is connected to FTM1 input channel 1.
1–0
ADHWTS
ADC Hardware Trigger Source
These bits select the ADC hardware trigger source. All trigger sources start ADC conversion on rising
edge.
00 RTC overflow as the ADC hardware trigger.
01 MTIM0 overflow as the ADC hardware trigger.
10 FTM2 init trigger with 8-bit programmable delay.
11 FTM2 match trigger with 8-bit programmable delay.
6.6.7 System Options Register 3 (SYS_SOPT3)
This register may be read and written at any time.
Address: 3000h base + 6h offset = 3006h
Bit 7 6 5 4 3 2 1 0
Read DLYACT 0
CLKOE BUSREF
Write
Reset
0 0 0 0 0 0 0 0
Chapter 6 System control
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 143