Datasheet

SYS_SOPT3 field descriptions
Field Description
7
DLYACT
FTM2 Trigger Delay Active
This read-only bit specifies the status if the FTM2 initial or match delay is active. This bit is set when an
FTM2 trigger arrives and the delay counter is ticking. Otherwise, this bit will be clear.
0 The delay inactive.
1 The delay active.
6–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
CLKOE
CLK Output Enable
This bit enables reference clock output on PTH2
0 ICSCLK output disabled on PTH2.
1 ICSCLK output enabled on PTH2.
2–0
BUSREF
BUS Output select
This bit enables bus clock output on PTH2 via an optional prescalar.
000 Bus.
001 Bus divided by 2.
010 Bus divided by 4.
011 Bus divided by 8.
100 Bus divided by 16.
101 Bus divided by 32.
110 Bus divided by 64.
111 Bus divided by 128.
6.6.8 System Options Register 4 (SYS_SOPT4)
Address: 3000h base + 7h offset = 3007h
Bit 7 6 5 4 3 2 1 0
Read
DELAY
Write
Reset
0 0 0 0 0 0 0 0
SYS_SOPT4 field descriptions
Field Description
7–0
DELAY
FTM2 Trigger Delay
These bits specify the delay from FTM2 initial or match trigger to ADC hardware trigger upon the setting of
ADHWT. The 8-bit modulo value allows the delay from 0 to 255 upon the BUSREF clock settings. This is a
one-shot counter that starts ticking when the trigger arrives and stop ticking when the counter value
reaches the modulo value that is defined.
System Control Registers
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
144 Freescale Semiconductor, Inc.