Datasheet

Chapter 7
Parallel input/output
7.1 Introduction
This device has eight sets of I/O ports, which include up to 57 general-purpose I/O pins.
Not all pins are available on all devices. See to determine which functions are available
for a specific device.
Many of the I/O pins are shared with on-chip peripheral functions, as shown in . The
peripheral modules have priority over the I/O, so when a peripheral is enabled, the
associated I/O functions are disabled.
After reset, the shared peripheral functions are disabled so that the pins are controlled by
the parallel I/O except PTA4 and PTA5 that are default to BKGD/MS and RESET
function. All of the parallel I/O are configured as high-impedance (Hi-Z). The pin control
functions for each pin are configured as follows:
• input disabled (PTxIEn = 0),
• output disabled (PTxOEn = 0), and
• internal pullups disabled (PTxPEn = 0).
Additionally, the parallel I/O that support high drive capability are disabled (HDRVE =
0x00) after reset.
The following three figures show the structures of each I/O pin.
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 151