Datasheet

1
0
PTxPEn
PTxOEn
PTxIEn
PTxDn
CPU read PTxDn
HDRVE
Figure 7-3. High drive I/O structure
7.2 Port data and data direction
Reading and writing of parallel I/O is accomplished through the port data registers
(PTxD). The direction, input or output, is controlled through the input enable or output
enable registers.
After reset, all parallel I/O default to the Hi-Z state. The corresponding bit in output
enable register (PTxOE) or input enable register (PTxIE) must be configured for output
or input operation. Each port pin has an input enable bit and an output enable bit. When
PTxIEn = 1, a read from PTxDn returns the input value of the associated pin; when
PTxIEn = 0, a read from PTxDn returns the last value written to the port data register.
NOTE
The PTxOE must be clear when the corresponding pin is used
as input function to avoid contention. If set the corresponding
PTxOE and PTxIE bits at same time, read from PTxDn will
always return the output data.
When a peripheral module or system function is in control of a port pin, the data direction
register bit still controls what is returned for reads of the port data register, even though
the peripheral system has overriding control of the actual pin direction.
Chapter 7 Parallel input/output
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 153