Datasheet

7.5 High current drive
Output high sink/source current drive can be enabled by setting the corresponding bit in
the HDRVE register for PTH1, PTH0, PTE1, PTE0, PTD1, PTD0, PTB5 and PTB4.
Output high sink/source current when they are operated as output. High current drive
function is disabled if the pin is configured as an input by the parallel I/O control logic.
When configured as any shared peripheral function, high current drive function still
works on these pins, but only when they are configured as outputs.
7.6 Pin behavior in stop mode
In stop3 mode, all I/O is maintained because internal logic circuitry stays powered up.
Upon recovery, normal I/O function is available to the user.
7.7 Port data registers
PORT memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
0 Port A Data Register (PORT_PTAD) 8 R/W 00h 7.7.1/156
1 Port B Data Register (PORT_PTBD) 8 R/W 00h 7.7.2/157
2 Port C Data Register (PORT_PTCD) 8 R/W 00h 7.7.3/157
3 Port D Data Register (PORT_PTDD) 8 R/W 00h 7.7.4/158
4 Port E Data Register (PORT_PTED) 8 R/W 00h 7.7.5/158
5 Port F Data Register (PORT_PTFD) 8 R/W 00h 7.7.6/159
6 Port G Data Register (PORT_PTGD) 8 R/W 00h 7.7.7/159
7 Port H Data Register (PORT_PTHD) 8 R/W 00h 7.7.8/160
30AF Port High Drive Enable Register (PORT_HDRVE) 8 R/W 00h 7.7.9/161
30B0 Port A Output Enable Register (PORT_PTAOE) 8 R/W 00h 7.7.10/162
30B1 Port B Output Enable Register (PORT_PTBOE) 8 R/W 00h 7.7.11/163
30B2 Port C Output Enable Register (PORT_PTCOE) 8 R/W 00h 7.7.12/164
30B3 Port D Output Enable Register (PORT_PTDOE) 8 R/W 00h 7.7.13/166
30B4 Port E Output Enable Register (PORT_PTEOE) 8 R/W 00h 7.7.14/167
30B5 Port F Output Enable Register (PORT_PTFOE) 8 R/W 00h 7.7.15/168
30B6 Port G Output Enable Register (PORT_PTGOE) 8 R/W 00h 7.7.16/169
30B7 Port H Output Enable Register (PORT_PTHOE) 8 R/W 00h 7.7.17/170
Table continues on the next page...
Chapter 7 Parallel input/output
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 155