Datasheet

PORT memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
30B8 Port A Input Enable Register (PORT_PTAIE) 8 R/W 00h 7.7.18/171
30B9 Port B Input Enable Register (PORT_PTBIE) 8 R/W 00h 7.7.19/172
30BA Port C Input Enable Register (PORT_PTCIE) 8 R/W 00h 7.7.20/173
30BB Port D Input Enable Register (PORT_PTDIE) 8 R/W 00h 7.7.21/175
30BC Port E Input Enable Register (PORT_PTEIE) 8 R/W 00h 7.7.22/176
30BD Port F Input Enable Register (PORT_PTFIE) 8 R/W 00h 7.7.23/177
30BE Port G Input Enable Register (PORT_PTGIE) 8 R/W 00h 7.7.24/178
30BF Port H Input Enable Register (PORT_PTHIE) 8 R/W 00h 7.7.25/179
30EC Port Filter Register 0 (PORT_IOFLT0) 8 R/W 00h 7.7.26/180
30ED Port Filter Register 1 (PORT_IOFLT1) 8 R/W 00h 7.7.27/181
30EE Port Filter Register 2 (PORT_IOFLT2) 8 R/W 00h 7.7.28/182
30EF Port Clock Division Register (PORT_FCLKDIV) 8 R/W 00h 7.7.29/183
30F0 Port A Pullup Enable Register (PORT_PTAPE) 8 R/W 00h 7.7.30/184
30F1 Port B Pullup Enable Register (PORT_PTBPE) 8 R/W 00h 7.7.31/185
30F2 Port C Pullup Enable Register (PORT_PTCPE) 8 R/W 00h 7.7.32/186
30F3 Port D Pullup Enable Register (PORT_PTDPE) 8 R/W 00h 7.7.33/188
30F4 Port E Pullup Enable Register (PORT_PTEPE) 8 R/W 00h 7.7.34/189
30F5 Port F Pullup Enable Register (PORT_PTFPE) 8 R/W 00h 7.7.35/190
30F6 Port G Pullup Enable Register (PORT_PTGPE) 8 R/W 00h 7.7.36/192
30F7 Port H Pullup Enable Register (PORT_PTHPE) 8 R/W 00h 7.7.37/193
7.7.1 Port A Data Register (PORT_PTAD)
Address: 0h base + 0h offset = 0h
Bit 7 6 5 4 3 2 1 0
Read
PTAD
Write
Reset
0 0 0 0 0 0 0 0
PORT_PTAD field descriptions
Field Description
7–0
PTAD
Port A Data Register Bits
For port A pins that are configured as inputs, a read returns the logic level on the pin.
For port A pins that are configured as outputs, a read returns the last value that was written to this register.
For port A pins that are configured as Hi-Z, a read returns uncertainty data.
Writes are latched into all bits of this register. For port A pins that are configured as outputs, the logic level
is driven out of the corresponding MCU pin.
Port data registers
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
156 Freescale Semiconductor, Inc.