Datasheet

PORT_PTCD field descriptions (continued)
Field Description
Reset forces PTCD to all 0s, but these 0s are not driven out of the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
7.7.4 Port D Data Register (PORT_PTDD)
Address: 0h base + 3h offset = 3h
Bit 7 6 5 4 3 2 1 0
Read
PTDD
Write
Reset
0 0 0 0 0 0 0 0
PORT_PTDD field descriptions
Field Description
7–0
PTDD
Port D Data Register Bits
For port D pins that are configured as inputs, a read returns the logic level on the pin.
For port D pins that are configured as outputs, a read returns the last value that was written to this
register.
For port D pins that are configured as Hi-Z, a read returns uncertainty data.
Writes are latched into all bits of this register. For port D pins that are configured as outputs, the logic level
is driven out of the corresponding MCU pin.
Reset forces PTDD to all 0s, but these 0s are not driven out of the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
7.7.5 Port E Data Register (PORT_PTED)
Address: 0h base + 4h offset = 4h
Bit 7 6 5 4 3 2 1 0
Read
PTED
Write
Reset
0 0 0 0 0 0 0 0
PORT_PTED field descriptions
Field Description
7–0
PTED
Port E Data Register Bits
For port E pins that are configured as inputs, a read returns the logic level on the pin.
For port E pins that are configured as outputs, a read returns the last value that was written to this register.
For port E pins that are configured as Hi-Z, a read returns uncertainty data.
Writes are latched into all bits of this register. For port E pins that are configured as outputs, the logic level
is driven out of the corresponding MCU pin.
Port data registers
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
158 Freescale Semiconductor, Inc.