Datasheet

PORT_PTED field descriptions (continued)
Field Description
Reset forces PTED to all 0s, but these 0s are not driven out of the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
7.7.6 Port F Data Register (PORT_PTFD)
Address: 0h base + 5h offset = 5h
Bit 7 6 5 4 3 2 1 0
Read
PTFD
Write
Reset
0 0 0 0 0 0 0 0
PORT_PTFD field descriptions
Field Description
7–0
PTFD
Port F Data Register Bits
For port F pins that are configured as inputs, a read returns the logic level on the pin.
For port F pins that are configured as outputs, a read returns the last value that was written to this register.
For port F pins that are configured as Hi-Z, a read returns uncertainty data.
Writes are latched into all bits of this register. For port F pins that are configured as outputs, the logic level
is driven out of the corresponding MCU pin.
Reset forces PTFD to all 0s, but these 0s are not driven out of the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
7.7.7 Port G Data Register (PORT_PTGD)
Address: 0h base + 6h offset = 6h
Bit 7 6 5 4 3 2 1 0
Read 0
PTGD
Write
Reset
0 0 0 0 0 0 0 0
PORT_PTGD field descriptions
Field Description
7–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3–0
PTGD
Port G Data Register Bits
For port G pins that are configured as inputs, a read returns the logic level on the pin.
For port G pins that are configured as outputs, a read returns the last value that was written to this
register.
Table continues on the next page...
Chapter 7 Parallel input/output
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 159