Datasheet
Section number Title Page
12.4.6 Edge-aligned PWM (EPWM) mode................................................................................................................334
12.4.7 Center-aligned PWM (CPWM) mode..............................................................................................................336
12.4.8 Combine mode.................................................................................................................................................338
12.4.8.1 Asymmetrical PWM......................................................................................................................345
12.4.9 Complementary mode......................................................................................................................................345
12.4.10 Update of the registers with write buffers........................................................................................................346
12.4.10.1 CNTINH:L registers......................................................................................................................346
12.4.10.2 MODH:L registers.........................................................................................................................346
12.4.10.3 CnVH:L registers...........................................................................................................................347
12.4.11 PWM synchronization......................................................................................................................................348
12.4.11.1 Hardware trigger............................................................................................................................348
12.4.11.2 Software trigger..............................................................................................................................349
12.4.11.3 Boundary cycle..............................................................................................................................350
12.4.11.4 MODH:L registers synchronization...............................................................................................351
12.4.11.5 CnVH:L registers synchronization.................................................................................................353
12.4.11.6 OUTMASK register synchronization............................................................................................353
12.4.11.7 FTM counter synchronization........................................................................................................355
12.4.11.8 Summary of PWM synchronization...............................................................................................357
12.4.12 Deadtime insertion...........................................................................................................................................359
12.4.12.1 Deadtime insertion corner cases....................................................................................................360
12.4.13 Output mask.....................................................................................................................................................362
12.4.14 Fault control.....................................................................................................................................................363
12.4.14.1 Automatic fault clearing.................................................................................................................365
12.4.14.2 Manual fault clearing.....................................................................................................................366
12.4.15 Polarity control.................................................................................................................................................366
12.4.16 Initialization.....................................................................................................................................................367
12.4.17 Features priority...............................................................................................................................................367
12.4.18 Channel trigger output.....................................................................................................................................367
12.4.19 Initialization trigger..........................................................................................................................................368
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
16 Freescale Semiconductor, Inc.