Datasheet

PORT_PTGD field descriptions (continued)
Field Description
For port G pins that are configured as Hi-Z, a read returns uncertainty data.
Writes are latched into all bits of this register. For port G pins that are configured as outputs, the logic level
is driven out of the corresponding MCU pin.
Reset forces PTGD to all 0s, but these 0s are not driven out of the corresponding pins because reset also
configures all port pins as high-impedance inputs with pullups disabled.
7.7.8 Port H Data Register (PORT_PTHD)
For port H pins that are configured as inputs, a read returns the logic level on the pin.
For port H pins that are configured as outputs, a read returns the last value that was
written to this register.
For port H pins that are configured as Hi-Z, a read returns uncertainty data.
Writes are latched into all bits of this register. For port H pins that are configured as
outputs, the logic level is driven out of the corresponding MCU pin.
Reset forces PTHD to all 0s, but these 0s are not driven out of the corresponding pins
because reset also configures all port pins as high-impedance inputs with pullups
disabled.
Address: 0h base + 7h offset = 7h
Bit 7 6 5 4 3 2 1 0
Read
PTHD7 PTHD6
0
PTHD2 PTHD1 PTHD0
Write
Reset
0 0 0 0 0 0 0 0
PORT_PTHD field descriptions
Field Description
7
PTHD7
Port H Data Register Bit 7
6
PTHD6
Port H Data Register Bit 6
5–3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
2
PTHD2
Port H Data Register Bit 2
1
PTHD1
Port H Data Register Bit 1
0
PTHD0
Port H Data Register Bit 0
Port data registers
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
160 Freescale Semiconductor, Inc.