Datasheet

7.7.9 Port High Drive Enable Register (PORT_HDRVE)
Address: 0h base + 30AFh offset = 30AFh
Bit 7 6 5 4 3 2 1 0
Read
PTH1 PTH0 PTE1 PTE0 PTD1 PTD0 PTB5 PTB4
Write
Reset
0 0 0 0 0 0 0 0
PORT_HDRVE field descriptions
Field Description
7
PTH1
PTH1
This read/write bit enables the high current drive capability of PTH1
0 PTH1 is disabled to offer high current drive capability.
1 PTH1 is enabled to offer high current drive capability.
6
PTH0
PTH0
This read/write bit enables the high current drive capability of PTH0
0 PTH0 is disabled to offer high current drive capability.
1 PTH0 is enabled to offer high current drive capability.
5
PTE1
PTE1
This read/write bit enables the high current drive capability of PTE1
0 PTE1 is disabled to offer high current drive capability.
1 PTE1 is enabled to offer high current drive capability.
4
PTE0
PTE0
This read/write bit enables the high current drive capability of PTE0
0 PTE0 is disabled to offer high current drive capability.
1 PTE0 is enable to offer high current drive capability.
3
PTD1
PTD1
This read/write bit enables the high current drive capability of PTD1
0 PTD1 is disabled to offer high current drive capability.
1 PTD1 is enable to offer high current drive capability.
2
PTD0
PTD0
This read/write bit enables the high current drive capability of PTD0
0 PTD0 is disabled to offer high current drive capability.
1 PTD0 is enable to offer high current drive capability.
1
PTB5
PTB5
This read/write bit enables the high current drive capability of PTB5
Table continues on the next page...
Chapter 7 Parallel input/output
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 161