Datasheet

PORT_PTFIE field descriptions (continued)
Field Description
0 Input disabled for port F bit 5.
1 Input enabled for port F bit 5.
4
PTFIE4
Input Enable for Port F Bit 4
This read/write bit enables the port F pin as an input.
0 Input disabled for port F bit 4.
1 Input enabled for port F bit 4.
3
PTFIE3
Input Enable for Port F Bit 3
This read/write bit enables the port F pin as an input.
0 Input disabled for port F bit 3.
1 Input enabled for port F bit 3.
2
PTFIE2
Input Enable for Port F Bit 2
This read/write bit enables the port F pin as an input.
0 Input disabled for port F bit 2.
1 Input enabled for port F bit 2.
1
PTFIE1
Input Enable for Port F Bit 1
This read/write bit enables the port F pin as an input.
0 Input disabled for port F bit 1.
1 Input enabled for port F bit 1.
0
PTFIE0
Input Enable for Port F Bit 0
This read/write bit enables the port F pin as an input.
0 Input disabled for port F bit 0.
1 Input enabled for port F bit 0.
7.7.24 Port G Input Enable Register (PORT_PTGIE)
Address: 0h base + 30BEh offset = 30BEh
Bit 7 6 5 4 3 2 1 0
Read 0
PTGIE3 PTGIE2 PTGIE1 PTGIE0
Write
Reset
0 0 0 0 0 0 0 0
PORT_PTGIE field descriptions
Field Description
7–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
Port data registers
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
178 Freescale Semiconductor, Inc.