Datasheet

PORT_PTGIE field descriptions (continued)
Field Description
3
PTGIE3
Input Enable for Port G Bit 3
This read/write bit enables the port G pin as an input.
0 Input disabled for port G bit 3.
1 Input enabled for port G bit 3.
2
PTGIE2
Input Enable for Port G Bit 2
This read/write bit enables the port G pin as an input.
0 Input disabled for port G bit 2.
1 Input enabled for port G bit 2.
1
PTGIE1
Input Enable for Port G Bit 1
This read/write bit enables the port G pin as an input.
0 Input disabled for port G bit 1.
1 Input enabled for port G bit 1.
0
PTGIE0
Input Enable for Port G Bit 0
This read/write bit enables the port G pin as an input.
0 Input disabled for port G bit 0.
1 Input enabled for port G bit 0.
7.7.25 Port H Input Enable Register (PORT_PTHIE)
Address: 0h base + 30BFh offset = 30BFh
Bit 7 6 5 4 3 2 1 0
Read
PTHIE7 PTHIE6
0
PTHIE2 PTHIE1 PTHIE0
Write
Reset
0 0 0 0 0 0 0 0
PORT_PTHIE field descriptions
Field Description
7
PTHIE7
Input Enable for Port H Bit 7
This read/write bit enables the port H pin as an input.
0 Input disabled for port H bit 7.
1 Input enabled for port H bit 7.
6
PTHIE6
Input Enable for Port H Bit 6
This read/write bit enables the port H pin as an input.
0 Input disabled for port H bit 6.
1 Input enabled for port H bit 6.
Table continues on the next page...
Chapter 7 Parallel input/output
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 179