Datasheet

PORT_IOFLT0 field descriptions (continued)
Field Description
3–2
FLTB
Filter selection for input from PTB
00 BUSCLK
01 FLTDIV1
10 FLTDIV2
11 FLTDIV3
1–0
FLTA
Filter selection for input from PTA
00 BUSCLK
01 FLTDIV1
10 FLTDIV2
11 FLTDIV3
7.7.27 Port Filter Register 1 (PORT_IOFLT1)
This register sets the filters for input from PTE to PTH.
Address: 0h base + 30EDh offset = 30EDh
Bit 7 6 5 4 3 2 1 0
Read
FLTH FLTG FLTF FLTE
Write
Reset
0 0 0 0 0 0 0 0
PORT_IOFLT1 field descriptions
Field Description
7–6
FLTH
Filter selection for input from PTH
00 BUSCLK
01 FLTDIV1
10 FLTDIV2
11 FLTDIV3
5–4
FLTG
Filter selection for input from PTG
00 BUSCLK
01 FLTDIV1
10 FLTDIV2
11 FLTDIV3
3–2
FLTF
Filter selection for input from PTF
00 BUSCLK
01 FLTDIV1
10 FLTDIV2
11 FLTDIV3
Table continues on the next page...
Chapter 7 Parallel input/output
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 181