Datasheet

7.7.29 Port Clock Division Register (PORT_FCLKDIV)
Configure the high/low level glitch width threshold. Glitches that are shorter than the
selected clock width will be filtered out; glitches that are more than twice the selected
clock width will not be filtered out (they will pass to the internal circuitry).
Address: 0h base + 30EFh offset = 30EFh
Bit 7 6 5 4 3 2 1 0
Read
FLTDIV3 FLTDIV2 FLTDIV1
Write
Reset
0 0 0 0 0 0 0 0
PORT_FCLKDIV field descriptions
Field Description
7–5
FLTDIV3
Filter Division Set 3
Port Filter Division Set 3
000 LPOCLK.
001 LPOCLK/2.
010 LPOCLK/4.
011 LPOCLK/8.
100 LPOCLK/16.
101 LPOCLK/32.
110 LPOCLK/64.
111 LPOCLK/128.
4–2
FLTDIV2
Filter Division Set 2
Port Filter Division Set 2
000 BUSCLK/32.
001 BUSCLK/64.
010 BUSCLK/128.
011 BUSCLK/256.
100 BUSCLK/512.
101 BUSCLK/1024.
110 BUSCLK/2048.
111 BUSCLK/4096.
1–0
FLTDIV1
Filter Division Set 1
Port Filter Division Set 1
00 BUSCLK/2.
01 BUSCLK/4.
10 BUSCLK/8.
11 BUSCLK/16.
Chapter 7 Parallel input/output
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 183