Datasheet

8.2 Internal clock source (ICS)
The internal clock source (ICS) module provides clock source options for the MCU. The
module contains a frequency-locked loop (FLL) as a clock source that is controllable by
an internal or external reference clock. The module can provide this FLL clock or the
internal reference clock as a source for the MCU system clock, ICSCLK.
Whichever clock source is chosen, ICSCLK is the output from a bus clock divider
(BDIV), which allows a lower clock frequency to be derived.
Key features of the ICS module are:
• Frequency-locked loop (FLL) is trimmable for accuracy
• Internal or external reference clocks can be used to control the FLL
• Reference divider is provided for external clock
• Internal reference clock has nine trim bits available
• Internal or external reference clocks can be selected as the clock source for the MCU
• Whichever clock is selected as the source can be divided down by 1, 2, 4, 8, 16, 32,
64 or 128
• FLL Engaged Internal mode is automatically selected out of reset
• A constant divide by 2 of the DCO output that can be select as BDC clock.
• Digitally-controlled oscillator (DCO) optimized for 16 MHz to 20 MHz frequency
range
• FLL lock detector and external clock monitor
• FLL lock detector with interrupt capability
• External reference clock monitor with reset capability
8.2.1 Function description
The following figure shows the ICS block diagram.
Chapter 8 Clock management
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 197