Datasheet

2
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2
n
2
n
IREFSTENIREFSTEN
ICSIRCLK
ICSOUT
ICSLCLK
Internal Clock Source Block
ICSFFCLK
DCOOUT
Filter
FLL
Internal
Reference
Clock
n=0-7
n=0-7
SCFTRIMSCTRIM
IREFST CLKST
IRCLKEN
DCO
LP
CLKS
BDIV
RDIV
IREFS
LOLIE LOLS LOCK CME
External Reference Clock /
Oscillator
ICSBDCCLK
CLKSW
BUSCLK
Figure 8-2. Internal clock source (ICS)
8.2.1.1 Bus frequency divider
The ICS_C2[BDIV] bits can be changed at anytime and the actual switch to the new
frequency occurs immediately.
8.2.1.2 Low power bit usage
The low power bit (ICS_C2[LP]) is provided to allow the FLL to be disabled and thus
conserve power when it is not used.
However, in some applications it may be desirable to allow the FLL to be enabled and to
lock for maximum accuracy before switching to an FLL engaged mode. To do this, write
the ICS_C2[LP] bit to 0.
8.2.1.3 Internal reference clock (ICSIRCLK)
When ICS_C1[IRCLKEN] is set the internal reference clock signal is presented as
ICSIRCLK, which can be used as an additional clock source. To re-target the ICSIRCLK
frequency, write a new value to the ICS_C3[SCTRIM] and ICS_C4[SCFTRIM] bits to
trim the period of the internal reference clock:
Internal clock source (ICS)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
198 Freescale Semiconductor, Inc.