Datasheet

• Writing a larger value slows down the ICSIRCLK frequency.
• Writing a smaller value to the ICSTRM register speeds up the ICSIRCLK frequency.
The TRIM bits affect the ICSOUT frequency if the ICS is in FLL engaged internal (FEI),
FLL bypassed internal (FBI), or FLL bypassed internal low power (FBILP) mode.
Until ICSIRCLK is trimmed, programming low reference divider (BDIV) factors may
result in ICSOUT frequencies that exceed the maximum chip-level frequency and violate
the chip-level clock timing specifications.
If ICS_C1[IREFSTEN] is set and the ICS_C1[IRCLKEN] bit is written to 1, the internal
reference clock keeps running during stop mode in order to provide a fast recovery upon
exiting stop.
All MCU devices are factory programmed with a trim value in a factory reserved
memory location. This value is uploaded to the ICS_C3 register and ICS_C4 register
during any reset initialization. For finer precision, trim the internal oscillator in the
application and set the ICS_C4[SCFTRIM] bit accordingly.
8.2.1.4 Fixed frequency clock (ICSFFCLK)
The ICS presents the divided FLL reference clock as ICSFFCLK for use as an additional
clock source. ICSFFCLK frequency must be no more than 1/4 of the ICSOUT frequency
to be valid. When ICSFFCLK is valid, ICS output signal (ICSFFE) gets asserted high.
Because of this requirement, in bypass modes the ICSFFCLK is valid only in bypass
external modes (FBE and FBELP) for the following combinations of BDIV, RDIV, and
RANGE values:
• RANGE=1
• BDIV=000 (divide by 1), RDIV ≥ 010
• BDIV=001 (divide by 2), RDIV ≥ 011
• BDIV=010 (divide by 4), RDIV ≥ 100
• BDIV=011 (divide by 8), RDIV ≥ 101
• BDIV=100 (divide by 16), NA
• BDIV=101 (divide by 32), NA
• BDIV=110 (divide by 64), NA
• BDIV=111 (divide by 128), NA
Chapter 8 Clock management
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 199