Datasheet

8.2.1.5 BDC clock
The ICS presents the DCO output clock divided by two as ICSLCLK for use as a clock
source for BDC communications. ICSLCLK is not available in FLL bypassed internal
low power (FBILP) and FLL bypassed external low power (FBELP) modes. The
ICSLCLK can be selected as BDC clock.
8.2.2 Modes of operation
There are seven modes of operation for the ICS: FEI, FEE, FBI, FBILP, FBE, FBELP,
and stop. The following figure shows the seven states of the ICS as a state diagram. The
arrows indicate the allowed movements between the states.
Returns to state that was active
before MCU entered stop, unless
RESET occurs while in stop.
Stop
IREFS=1
CLKS=00
FLL Bypassed
Internal Low
Power(FBILP)
IREFS=1
CLKS=01
BDM Disabled
and LP=1
IREFS=1
CLKS=01
BDM Enabled
or LP=0
IREFS=0
CLKS=10
BDM Disabled
and LP=1
FLL Bypassed
External Low
Power(FBELP)
FLL Engaged
Internal (FEI)
FLL Bypassed
External (FBE)
FLL Engaged
External (FEE)
Internal (FBI)
IREFS=0
CLKS=00
IREFS=0
CLKS=10
BDM Enabled
or LP =0
FLL Bypassed
Entered from any state
when MCU enters stop
Figure 8-3. ICS clocking switching modes
The ICS_C1[IREFS] bit can be changed at anytime, but the actual switch to the newly
selected clock is shown by the ICS_S[IREFST] bit. When switching between FLL
engaged internal (FEI) and FLL engaged external (FEE) modes, the FLL will lock again
after the switch is completed.
Internal clock source (ICS)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
200 Freescale Semiconductor, Inc.