Datasheet

The ICS_C1[CLKS] bits can also be changed at anytime, but the actual switch to the
newly selected clock is shown by the ICS_S[CLKST] bits. If the newly selected clock is
not available, the previous clock remains selected.
8.2.2.1 FLL engaged internal (FEI)
FLL engaged internal (FEI) is the default mode of operation and is entered when all of
the following conditions occur:
• ICS_C1[CLKS] bits are written to 0b
• ICS_C1[IREFS] bit is written to 1b
In FLL engaged internal mode, the ICSOUT clock is derived from the FLL clock, which
is controlled by the internal reference clock. The FLL loop locks the frequency to the 512
times the internal reference frequency. The ICSLCLK is available for BDC
communications, and the internal reference clock is enabled.
8.2.2.2 FLL engaged external (FEE)
The FLL engaged external (FEE) mode is entered when all of the following conditions
occur:
• ICS_C1[CLKS] bits are written to 00b
• ICS_C1[IREFS] bit written to 0b
• ICS_C1[RDIV] bits are written to divide external reference clock to be within the
range of 31.25 kHz to 39.0625 kHz
In FLL engaged external mode, the ICSOUT clock is derived from the FLL clock, which
is controlled by the external reference clock source. The FLL loop locks the frequency to
the 512 times the external reference frequency, as selected by the ICS_C1[RDIV] bits.
The ICSLCLK is available for BDC communications, and the external reference clock is
enabled.
8.2.2.3 FLL bypassed internal (FBI)
The FLL bypassed internal (FBI) mode is entered when all of the following conditions
occur:
Chapter 8 Clock management
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 201