Datasheet

• ICS_C1[CLKS] bits are written to 01
• ICS_C1[IREFS] bit is written to 1
• BDM mode is active or ICS_C2[LP] bit is written to 0
In FLL bypassed internal mode, the ICSOUT clock is derived from the internal reference
clock. The FLL clock is controlled by the internal reference clock, and the FLL loop
locks the FLL frequency to the 512 times the internal reference frequency. The ICSLCLK
will be available for BDC communications, and the internal reference clock is enabled.
8.2.2.4 FLL bypassed internal low power (FBILP)
The FLL bypassed internal low power (FBILP) mode is entered when all the following
conditions occur:
• ICS_C1[CLKS] bits are written to 01
• ICS_C1[IREFS] bit is written to 1
• BDM mode is not active and ICS_C2[LP] bit is written to 1
In FLL bypassed internal low power mode, the ICSOUT clock is derived from the
internal reference clock and the FLL is disabled. The ICSLCLK will be not be available
for BDC communications, and the internal reference clock is enabled.
8.2.2.5 FLL bypassed external (FBE)
The FLL bypassed external (FBE) mode is entered when all of the following conditions
occur:
• ICS_C1[CLKS] bits are written to 10
• ICS_C1[IREFS] bit is written to 0
• ICS_C1[RDIV] bits are written to divide external reference clock to be within the
range of 31.25 kHz to 39.0625 kHz
• BDM mode is active or ICS_C2[LP] bit is written to 0
Internal clock source (ICS)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
202 Freescale Semiconductor, Inc.