Datasheet

In FLL bypassed external mode, the ICSOUT clock is derived from the external reference
clock source. The FLL clock is controlled by the external reference clock, and the FLL
loop locks the FLL frequency to the 512 times the external reference frequency, as
selected by the ICS_C1[RDIV] bits, so that the ICSLCLK will be available for BDC
communications, and the external reference clock is enabled.
8.2.2.6 FLL bypassed external low power (FBELP)
The FLL bypassed external low power (FBELP) mode is entered when all of the
following conditions occur:
• ICS_C1[CLKS] bits are written to 10
• ICS_C1[IREFS] bit is written to 0
• BDM mode is not active and ICS_C2[LP] bit is written to 1
In FLL bypassed external low power mode, the ICSOUT clock is derived from the
external reference clock source and the FLL is disabled. The ICSLCLK will be not
available for BDC communications. The external reference clock source is enabled.
8.2.2.7 Stop (STOP)
In stop mode, the FLL is disabled and the internal clock source can be enabled or
disabled. The BDC clock is not available and the ICS does not provide MCU clock
source.
Stop mode is entered whenever the MCU enters a stop state. In this mode, all ICS clock
signals are static except in the following cases:
• ICSIRCLK will be active in stop mode when all of the following conditions occur:
• ICS_C1[IRCLKEN] bit is written to 1
• ICS_C1[IREFSTEN] bit is written to 1
• OSCOUT will be active in stop mode when all of the following conditions occur:
• ICS_OSCSC[OSCEN] bit is written to 1
• ICS_OSCSC[OSCSTEN] bit is written to 1
NOTE
The DCO frequency changes from the pre-stop value to its reset
value and the FLL need to re-acquire the lock before the
Chapter 8 Clock management
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 203