Datasheet

frequency is stable. Timing sensitive operations must wait for

the FLL acquisition time, t

Aquire

, before executing.

FLL lock and clock monitor

8.2.3.1 FLL clock lock

In FBE and FEE modes, the clock detector source uses the external reference as the

reference. When FLL is detected from lock to unlock, the ICS_S[LOLS] bit is set. An

interrupt will be generated if ICS_C4[LOLIE] bit is set. ICS_S[LOLS] bit is cleared by

reset or by writing a logic 1 to ICS_S[LOLS] when ICS_S[LOLS] is set. Writing a logic

0 to ICS_S[LOLS] has no effect.

In FBI and FEI modes, the lock detector source uses the internal reference as the

reference. When FLL is detected from lock to unlock, the ICS_S[LOLS] bit is set. An

interrupt will be generated if ICS_S[LOLS] bit is set. ICS_S[LOLS] bit is cleared by

reset or by writing a logic 1 to ICS_S[LOLS] when ICS_S[LOLS] is set. Writing a logic

0 to ICS_S[LOLS] has no effect.

In FBELP and FBILP modes, the FLL is not on, therefore, lock detect function is not

applicable.

8.2.3.2 External reference clock monitor

In FBE, FEE, FEI, or FBI modes, if ICS_C4[CME] bit is written to 1, the clock monitor

is enabled. If the external reference falls below a certain frequency, such as f

loc_high

loc_low

depending on the ICS_OSCSC[RANGE] bit, the MCU will reset. The

SYS_SRS[CLK] bit will be set to indicate the error.

In FBELP or FBILP modes, the FLL is not on, so the external reference clock monitor

will not function even if ICS_C4[CME] bit is written to 1.

External reference clock monitor uses FLL as the internal reference clock. The FLL must

be functional before ICS_C4[CME] bit is set.

8.3 Initialization / application information

This section provides example code to give some basic direction to a user on how to

initialize and configure the ICS module. The example software is implemented in C

language.

8.2.3

FLL lock and clock monitor

MC9S08PA60 Reference Manual, Rev. 1, 9/2012

204 Freescale Semiconductor, Inc.