Datasheet

ICS memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
3038 ICS Control Register 1 (ICS_C1) 8 R/W 04h 8.6.1/210
3039 ICS Control Register 2 (ICS_C2) 8 R/W 20h 8.6.2/211
303A ICS Control Register 3 (ICS_C3) 8 R/W Undefined 8.6.3/212
303B ICS Control Register 4 (ICS_C4) 8 R/W 00h 8.6.4/212
303C ICS Status Register (ICS_S) 8 R 10h 8.6.5/213
303E OSC Status and Control Register (ICS_OSCSC) 8 R/W 00h 8.6.6/214
8.6.1 ICS Control Register 1 (ICS_C1)
Address: 3038h base + 0h offset = 3038h
Bit 7 6 5 4 3 2 1 0
Read
CLKS RDIV IREFS IRCLKEN IREFSTEN
Write
Reset
0 0 0 0 0 1 0 0
ICS_C1 field descriptions
Field Description
7–6
CLKS
Clock Source Select
Selects the clock source that controls the bus frequency. The actual bus frequency depends on the value
of the BDIV bits.
00 Output of FLL is selected.
01 Internal reference clock is selected.
10 External reference clock is selected.
11 Reserved, defaults to 00.
5–3
RDIV
Reference Divider
Selects the amount to divide down the FLL reference clock selected by the IREFS bits. Resulting
frequency must be in the range 31.25 kHz to 39.0625 kHz.
RDIV ICS_OSCSC[RANGE]= 0 ICS_OSCSC[RANGE]= 1
000 1
1
32
001 2 64
010 4 128
011 8 256
100 16 512
101 32 1024
110 64 Reserved
111 128 Reserved
Table continues on the next page...
ICS control registers
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
210 Freescale Semiconductor, Inc.