Datasheet

ICS_C2 field descriptions (continued)
Field Description
4
LP
Low Power Select
The LP bit controls whether the FLL is disabled in FLL bypassed modes.
0 FLL is not disabled in bypass mode.
1 FLL is disabled in bypass modes unless BDM is active.
3–0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
8.6.3 ICS Control Register 3 (ICS_C3)
Address: 3038h base + 2h offset = 303Ah
Bit 7 6 5 4 3 2 1 0
Read
SCTRIM
Write
Reset
x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.•
ICS_C3 field descriptions
Field Description
7–0
SCTRIM
Slow Internal Reference Clock Trim Setting
The SCTRIM bits control the slow internal reference clock frequency by controlling the internal reference
clock period. The bits are binary weighted. In other words, bit 1 adjusts twice as much as bit 0. Increasing
the binary value in SCTRIM will increase the period, and decreasing the value will decrease the period. An
additional fine trim bit is available in ICSC4 as the SCFTRIM bit.
8.6.4 ICS Control Register 4 (ICS_C4)
Address: 3038h base + 3h offset = 303Bh
Bit 7 6 5 4 3 2 1 0
Read
LOLIE
0
CME
0
SCFTRIM
Write
Reset
0 0 0 0 0 0 0 0
ICS_C4 field descriptions
Field Description
7
LOLIE
Loss of Lock Interrupt
Determines if an interrupt request is made following a loss of lock indication. The LOLIE bit has an effect
only when LOLS is set.
Table continues on the next page...
ICS control registers
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
212 Freescale Semiconductor, Inc.