Datasheet

ICS_OSCSC field descriptions (continued)
Field Description
5
OSCSTEN
OSC Enable in Stop mode
The OSCSTEN bit controls whether or not the OSC clock remains enabled when MCU enters stop mode.
0 OSC clock is disabled in stop.
1 OSC stays enabled in stop if OSCEN is set or if ICS is set or ICS requests to be active before entering
stop.
4
OSCOS
OSC Output Select
This bit is used to select the output clock of OSC module.
0 External clock source from EXTAL pin is selected.
1 Oscillator clock source is selected.
3
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
2
RANGE
Frequency Range Select
Selects the frequency range for the OSC module.
0 Low frequency range of 31.25kHz - 39.0625kHz.
1 High frequency range of 4 - 20MHz.
1
HGO
High Gain Oscillator Select
The HGO bit controls the OSC mode of operation.
0 Low gain mode.
1 High gain mode.
0
OSCINIT
OSC Initialization
This bit set after the initialization cycles of oscillator completes.
0 Oscillator initialization not completes.
1 Oscillator initialization completed.
8.7 System clock gating control registers
SCG memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
300C System Clock Gating Control 1 Register (SCG_C1) 8 R/W E7h 8.7.1/216
300D System Clock Gating Control 2 Register (SCG_C2) 8 R/W 3Ch 8.7.2/217
300E System Clock Gating Control 3 Register (SCG_C3) 8 R/W 7Eh 8.7.3/218
300F System Clock Gating Control 4 Register (SCG_C4) 8 R/W ABh 8.7.4/219
Chapter 8 Clock management
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 215