Datasheet

SCG_C2 field descriptions (continued)
Field Description
0 Bus clock to the NVM module is disabled.
1 Bus clock to the NVM module is enabled.
3
IPC
IPC Clock Gate Control
This bit controls the clock gate to the IPC module.
0 Bus clock to the IPC module is disabled.
1 Bus clock to the IPC module is enabled.
2
CRC
CRC Clock Gate Control
This bit controls the clock gate to the CRC module.
0 Bus clock to the CRC module is disabled.
1 Bus clock to the CRC module is enabled.
1–0
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
8.7.3 System Clock Gating Control 3 Register (SCG_C3)
This high page register contains control bits to enable or disable the bus clock to the SCI,
SPI, IIC modules. Gating off the clocks to unused peripherals is used to reduce the
MCU's run and wait currents.
NOTE
User software should disable the peripheral before disabling the
clocks to the peripheral. When clocks are re-enabled to a
peripheral, the peripheral registers need to be re-initialized by
user software.
Address: 300Ch base + 2h offset = 300Eh
Bit 7 6 5 4 3 2 1 0
Read 0
SCI2 SCI1 SCI0 SPI1 SPI0 IIC
0
Write
Reset
0 1 1 1 1 1 1 0
SCG_C3 field descriptions
Field Description
7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
6
SCI2
SCI2 Clock Gate Control
This bit controls the clock gate to the SCI2 module.
Table continues on the next page...
System clock gating control registers
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
218 Freescale Semiconductor, Inc.