Datasheet
Section number Title Page
17.3 Memory Map and Register Descriptions........................................................................................................................459
17.3.1 SPI control register 1 (SPIx_C1)......................................................................................................................459
17.3.2 SPI control register 2 (SPIx_C2)......................................................................................................................461
17.3.3 SPI baud rate register (SPIx_BR).....................................................................................................................463
17.3.4 SPI status register (SPIx_S).............................................................................................................................464
17.3.5 SPI data register high (SPIx_DH)....................................................................................................................467
17.3.6 SPI data register low (SPIx_DL)......................................................................................................................467
17.3.7 SPI match register high (SPIx_MH)................................................................................................................468
17.3.8 SPI match register low (SPIx_ML)..................................................................................................................468
17.3.9 SPI control register 3 (SPIx_C3)......................................................................................................................469
17.3.10 SPI clear interrupt register (SPIx_CI)..............................................................................................................470
17.4 Functional Description....................................................................................................................................................472
17.4.1 General.............................................................................................................................................................472
17.4.2 Master Mode....................................................................................................................................................473
17.4.3 Slave Mode......................................................................................................................................................474
17.4.4 SPI FIFO Mode................................................................................................................................................475
17.4.5 Data Transmission Length...............................................................................................................................476
17.4.6 SPI Clock Formats...........................................................................................................................................477
17.4.7 SPI Baud Rate Generation...............................................................................................................................480
17.4.8 Special Features...............................................................................................................................................481
17.4.8.1 SS Output.......................................................................................................................................481
17.4.8.2 Bidirectional Mode (MOMI or SISO)...........................................................................................481
17.4.9 Error Conditions...............................................................................................................................................482
17.4.9.1 Mode Fault Error............................................................................................................................483
17.4.10 Low Power Mode Options...............................................................................................................................483
17.4.10.1 SPI in Run Mode............................................................................................................................483
17.4.10.2 SPI in Wait Mode...........................................................................................................................483
17.4.10.3 SPI in Stop Mode...........................................................................................................................484
17.4.11 Reset.................................................................................................................................................................485
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
22 Freescale Semiconductor, Inc.