Datasheet

Address: 300Ch base + 3h offset = 300Fh
Bit 7 6 5 4 3 2 1 0
Read
ACMP
0
ADC
0
IRQ
0
KBI1 KBI0
Write
Reset
1 0 1 0 1 0 1 1
SCG_C4 field descriptions
Field Description
7
ACMP
ACMP Clock Gate Control
This bit controls the clock gate to the ACMP module.
0 Bus clock to the ACMP module is disabled.
1 Bus clock to the ACMP module is enabled.
6
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
5
ADC
ADC Clock Gate Control
This bit controls the clock gate to the ADC module.
0 Bus clock to the ADC module is disabled.
1 Bus clock to the ADC module is enabled.
4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
IRQ
IRQ Clock Gate Control
This bit controls the clock gate to the IRQ module.
0 Bus clock to the IRQ module is disabled.
1 Bus clock to the IRQ module is enabled.
2
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
1
KBI1
KBI1 Clock Gate Control
This bit controls the clock gate to the KBI1 module.
0 Bus clock to the KBI1 module is disabled.
1 Bus clock to the KBI1 module is enabled.
0
KBI0
KBI0 Clock Gate Control
This bit controls the clock gate to the KBI0 module.
0 Bus clock to the KBI0 module is disabled.
1 Bus clock to the KBI0 module is enabled.
System clock gating control registers
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
220 Freescale Semiconductor, Inc.