Datasheet

Chapter 9
Chip configurations
9.1 Introduction
This chapter provides details on the individual modules of the device. It includes:
• device block diagrams highlighting the specific modules and pin-outs
• specific module-to-module interactions not necessarily discussed in the individual
module chapters, and
• links for more information
Core modules
9.2.1 Central processor unit (CPU)
The HCS08 CPU is fully source- and object-code-compatible with the M68HC08 CPU.
Several instructions and enhanced addressing modes were added to improve C compiler
efficiency and to support a new background debug system which replaces the monitor
mode of earlier M68HC08 microcontrollers.
9.2.2 Debug module (DBG)
The DBG module implements an on-chip ICE (in-circuit emulation) system and allows
non-intrusive debug of application software by providing an on-chip trace buffer with
flexible triggering capability. The trigger can also provide extended breakpoint capacity.
The on-chip ICE system is optimized for the HCS08 8-bit architecture and supports 64
KB of memory space.
9.2
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