Datasheet

9.8.1.1 FTM0 interconnection
SCI0 TxD signal can be modulated by FTM0 channel 0 PWM output. Please refer to
SCI0 TxD modulation.
SCI0 RxD signal can be tagged by FTM0 channel 1 input capture function. Please refer
to SCI0 RxD filter.
9.8.1.2 FTM1 interconnection
ACMP output can be internally connected to FTM1 channel 0 capture input. See ACMP
output selection for details.
9.8.1.3 FTM2 interconnection
FTM2 supports three PWM synchronization sources:
• Trigger0 is connected to the output of ACMP.
• Trigger1 is connected to FTM0 channel 0 output.
• Trigger2 is a software trigger by writing 1 to the SYS_SOPT2[FTMSYNC] bit.
Please refer to System interconnection.
FTM2 supports four FTM fault sources:
• Fault 0 is connected to ACMP output.
• Fault1 is connected to PTA6.
• Fault 2 is connected to PTA7.
• Fault 3 is not used. Please refer to System interconnection.
FTM2 supports seven FTM triggers including an initialization trigger and six channel
triggers to other modules. The initialization trigger and match trigger are optionally
connected to ADC hardware trigger via an 8-bit delay counter. All other triggers are not
used in this device. Please refer to System interconnection.
9.8.2 8-bit modulo timer (MTIM)
MTIM0 8-bit modulo timer module that provide a circuit of selectable clock sources and
a programmable interrupt. The MTIM module contain an 8-bit modulo counter, which
can operate as a free-running counter or a modulo counter. A timer overflow interrupt can
be enabled to generate periodic interrupts for time-based software events. MTIM module
may also use external clock source.
Chapter 9 Chip configurations
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 229