Datasheet

Section number Title Page
18.3.12 I2C SCL Low Timeout Register Low (I2C_SLTL).........................................................................................506
18.4 Functional description.....................................................................................................................................................506
18.4.1 I2C protocol.....................................................................................................................................................506
18.4.1.1 START signal................................................................................................................................507
18.4.1.2 Slave address transmission.............................................................................................................507
18.4.1.3 Data transfers.................................................................................................................................508
18.4.1.4 STOP signal...................................................................................................................................508
18.4.1.5 Repeated START signal.................................................................................................................508
18.4.1.6 Arbitration procedure.....................................................................................................................509
18.4.1.7 Clock synchronization....................................................................................................................509
18.4.1.8 Handshaking...................................................................................................................................510
18.4.1.9 Clock stretching.............................................................................................................................510
18.4.1.10 I2C divider and hold values...........................................................................................................510
18.4.2 10-bit address...................................................................................................................................................511
18.4.2.1 Master-transmitter addresses a slave-receiver...............................................................................512
18.4.2.2 Master-receiver addresses a slave-transmitter...............................................................................512
18.4.3 Address matching.............................................................................................................................................513
18.4.4 System management bus specification............................................................................................................514
18.4.4.1 Timeouts.........................................................................................................................................514
18.4.4.2 FAST ACK and NACK.................................................................................................................516
18.4.5 Resets...............................................................................................................................................................516
18.4.6 Interrupts..........................................................................................................................................................516
18.4.6.1 Byte transfer interrupt....................................................................................................................517
18.4.6.2 Address detect interrupt.................................................................................................................517
18.4.6.3 Exit from low-power/stop modes...................................................................................................517
18.4.6.4 Arbitration lost interrupt................................................................................................................517
18.4.6.5 Timeout interrupt in SMBus..........................................................................................................518
18.4.7 Programmable input glitch filter......................................................................................................................518
18.4.8 Address matching wakeup...............................................................................................................................519
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
24 Freescale Semiconductor, Inc.