Datasheet

10.2.4 Program Counter (PC)
The program counter is a 16-bit register that contains the address of the next instruction
or operand to be fetched.
During normal program execution, the program counter automatically increments to the
next sequential memory location every time an instruction or operand is fetched. Jump,
branch, interrupt, and return operations load the program counter with an address other
than that of the next sequential location. This is called a change-of-flow.
During reset, the program counter is loaded with the reset vector that is located at
0xFFFE and 0xFFFF. The vector stored there is the address of the first instruction that
will be executed after exiting the reset state.
10.2.5 Condition Code Register (CCR)
The 8-bit condition code register contains the interrupt mask (I) and five flags that
indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1.
The following paragraphs describe the functions of the condition code bits in general
terms.
Table 10-1. CCR Register Field Descriptions
Field Description
7
V
Two's Complement Overflow Flag — The CPU sets the overflow flag when a two's complement
overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag.
0 No overflow
1 Overflow
4
H
Half-Carry Flag — The CPU sets the half-carry flag when a carry occurs between accumulator bits
3 and 4 during an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is
required for binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states
of the H and C condition code bits to automatically add a correction value to the result from a
previous ADD or ADC on BCD operands to correct the result to a valid BCD value.
0 No carry between bits 3 and 4
1 Carry between bits 3 and 4
Table continues on the next page...
Programmer's Model and CPU Registers
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
254 Freescale Semiconductor, Inc.