Datasheet

10.4.4 Security mode
Usually HCS08 V6 MCUs are implemented with a secure operating mode. When in
secure mode, external access to internal memory is restricted, so that only instructions
fetched from secure memory can access secure memory.
The method by which the MCU is put into secure mode is not defined by the HCS08 V6
Core. The core receives an external input signal that, when asserted, informs to the core
that the MCU is in secure mode.
While in secure mode, the core controls the following set of conditions:
1. The RAM, flash, and EEPROM arrays are considered secure memory. All registers
in Direct Page or High Page are considered non-secure memory.
2. Read data is tagged as either secure or non-secure during a program read, depending
on whether the read is from secure or non-secure memory.
3. A data read of secure memory returns a value of $00 when the current instruction is
tagged as non-secure or the access is a BDC access.
4. A data write to secure memory is blocked and data at the target address does not
change state when the current instruction is tagged as non-secure or the access is
through BDC.
5. A data write to secure memory is never blocked during the stacking cycles of
interrupt service routines.
6. Data accesses to either secure or non-secure memory are allowed when the current
instruction is tagged as secure.
7. BDC accesses to non-secure memory are allowed.
When the device is in the non-secure mode, secure memory is treated the same as non-
secure memory, and all accesses are allowed.
Table 10-2 details the security conditions for allowing or disabling a read access.
Table 10-2. Security conditions for read access
Inputs conditions Read control
Security
enabled
Ram, flash or
EEPROM
access
Program or
vector read
Current CPU instruction
from secure memory
Current access
is via BDC
Read access
allowed
0 x x x x 1
1 0 x x x 1
1 1 1 x x 1
Table continues on the next page...
Operation modes
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
264 Freescale Semiconductor, Inc.