Datasheet

10.6.2 Interrupt Sequence
When an interrupt is requested, the CPU completes the current instruction before
responding to the interrupt. At this point, the program counter is pointing at the start of
the next instruction, which is where the CPU should return after servicing the interrupt.
The CPU responds to an interrupt by performing the same sequence of operations as for a
software interrupt (SWI) instruction, except the address used for the vector fetch is
determined by the highest priority interrupt that is pending when the interrupt sequence
started.
The CPU sequence for an interrupt is:
1. Store the contents of PCL, PCH, X, A, and CCR on the stack, in that order.
2. Set the I bit in the CCR.
3. Fetch the high-order half of the interrupt vector.
4. Fetch the low-order half of the interrupt vector.
5. Delay for one free bus cycle.
Fetch three bytes of program information starting at the address indicated by the interrupt
vector to fill the instruction queue in preparation for execution of the first instruction in
the interrupt service routine.
After the CCR contents are pushed onto the stack, the I bit in the CCR is set to prevent
other interrupts while in the interrupt service routine. Although it is possible to clear the I
bit with an instruction in the interrupt service routine, this would allow nesting of
interrupts (which is not recommended because it leads to programs that are difficult to
debug and maintain).
For compatibility with the earlier M68HC05 MCUs, the high-order half of the H:X index
register pair (H) is not saved on the stack as part of the interrupt sequence. The user must
use a PSHH instruction at the beginning of the service routine to save H and then use a
PULH instruction just before the RTI that ends the interrupt service routine. It is not
necessary to save H if you are certain that the interrupt service routine does not use any
instructions or auto-increment addressing modes that might change the value of H.
The software interrupt (SWI) instruction is like a hardware interrupt except that it is not
masked by the global I bit in the CCR and it is associated with an instruction opcode
within the program so it is not asynchronous to program execution.
Special Operations
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
266 Freescale Semiconductor, Inc.