Datasheet

10.7 Instruction Set Summary
Table 10-3. Instruction Set Summary
Source Form Operation Description
Effect on CCR
Address
Mode
Opcode
Operand
Bus Cycles
V H I N Z C
ADC #opr8i ↕ ↕ – ↕ ↕ ↕ IMM A9 ii 2
ADC opr8a ↕ ↕ – ↕ ↕ ↕ DIR B9 dd 3
ADC opr16a ↕ ↕ – ↕ ↕ ↕ EXT C9 hh ll 4
ADC oprx16,X ↕ ↕ – ↕ ↕ ↕
IX2 D9 ee ff 4
ADC oprx8,X
Add with Carry A ← (A) + (M) + (C)
↕ ↕ – ↕ ↕ ↕ IX1 E9 ff 3
ADC ,X ↕ ↕ – ↕ ↕ ↕ IX F9 3
ADC oprx16,SP ↕ ↕ – ↕ ↕ ↕ SP2 9ED9 ee ff 5
ADC oprx8,SP ↕ ↕ – ↕ ↕ ↕ SP1 9EE9 ff 4
ADD #opr8i ↕ ↕ – ↕ ↕ ↕ IMM AB ii 2
ADD opr8a ↕ ↕ – ↕ ↕ ↕ DIR BB dd 3
ADD opr16a ↕ ↕ – ↕ ↕ ↕ EXT CB hh ll 4
ADD oprx16,X ↕ ↕ – ↕ ↕ ↕ IX2 DB ee ff 4
ADD oprx8,X
Add without Carry A ← (A) + (M)
↕ ↕ – ↕ ↕ ↕ IX1 EB ff 3
ADD ,X ↕ ↕ – ↕ ↕ ↕ IX FB 3
ADD oprx16,SP ↕ ↕ – ↕ ↕ ↕ SP2 9EDB ee ff 5
ADD oprx8,SP ↕ ↕ – ↕ ↕ ↕ SP1 9EEB ff 4
AIS #opr8i Add Immediate Value
(Signed) to Stack
Pointer
SP ← (SP) + (M) where
M is sign extended to a
16-bit value
– – – – – – IMM A7 ii 2
AIX #opr8i Add Immediate Value
(Signed) to Index
Register (H:X)
H:X ← (H:X) + (M)
where M is sign
extended to a 16-bit
value
– – – – – – IMM AF ii 2
AND #opr8i 0 – – ↕ ↕ – IMM A4 ii 2
AND opr8a 0 – – ↕ ↕ – DIR B4 dd 3
AND opr16a 0 – – ↕ ↕ – EXT C4 hh ll 4
AND oprx16,X 0 – – ↕ ↕ – IX2 D4 ee ff 4
AND oprx8,X
Logical AND A ← (A) & (M)
0 – – ↕ ↕ – IX1 E4 ff 3
AND ,X 0 – – ↕ ↕ – IX F4 3
AND oprx16,SP 0 – – ↕ ↕ – SP2 9ED4 ee ff 5
AND oprx8,SP 0 – – ↕ ↕ – SP1 9EE4 ff 4
ASL opr8a ↕ – – ↕ ↕ ↕ DIR 38 dd 5
ASLA ↕ – – ↕ ↕ ↕ INH 48 1
ASLX ↕ – – ↕ ↕ ↕ INH 58 1
Table continues on the next page...
Chapter 10 Central processor unit
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 267