Datasheet

Table 10-3. Instruction Set Summary (continued)
Source Form Operation Description
Effect on CCR
Address
Mode
Opcode
Operand
Bus Cycles
V H I N Z C
ASL oprx8,X Arithmetic Shift Left
(same as LSL)
C ← MSB, LSB ← 0 ↕ – – ↕ ↕ ↕ IX1 68 ff 5
ASL ,X ↕ – – ↕ ↕ ↕ IX 78 4
ASL oprx8,SP ↕ – – ↕ ↕ ↕ SP1 9E68 ff 6
ASR opr8a ↕ – – ↕ ↕ ↕ DIR 37 dd 5
ASRA ↕ – – ↕ ↕ ↕ INH 47 1
ASRX ↕ – – ↕ ↕ ↕ INH 57 1
ASR oprx8,X
Arithmetic Shift Right MSB → MSB, LSB → C
↕ – – ↕ ↕ ↕ IX1 67 ff 5
ASR ,X ↕ – – ↕ ↕ ↕ IX 77 4
ASR oprx8,SP ↕ – – ↕ ↕ ↕ SP1 9E67 ff 6
BCC rel Branch if Carry Bit
Clear
Branch if (C) = 0 – – – – – – REL 24 rr 3
– – – – – – DIR (b0) 11 dd 5
– – – – – – DIR (b1) 13 dd 5
– – – – – – DIR (b2) 15 dd 5
BCLR n,opr8a
Clear Bit n in Memory Mn ← 0
– – – – – – DIR (b3) 17 dd 5
– – – – – – DIR (b4) 19 dd
– – – – – – DIR (b5) 1B dd
5
– – – – – – DIR (b6) 1D dd 5
– – – – – – DIR (b7) 1F dd 5
BCS rel Branch if Carry Bit Set
(same as BLO)
Branch if (C) = 1 – – – – – – REL 25 rr 3
BEQ rel Branch if Equal Branch if (Z) = 1 – – – – – – REL 27 rr 3
BGE rel Branch if Greater
Than or Equal To
(Signed Operands)
Branch if (N ⊕ V) = 0 – – – – – – REL 90 rr 3
BGND Enter Active
Background if ENBDM
= 1
Waits For and
Processes BDM
Commands Until GO,
TRACE1, or TAGGO
– – – – – – INH 82 5+
BGT rel Branch if Greater
Than (Signed
Operands)
Branch if (Z) | (N ⊕ V) =
0
− − − − − − REL 92 rr 3
BHCC rel Branch if Half Carry
Bit Clear
Branch if (H) = 0 − − − − − − REL 28 rr 3
BHCS rel Branch if Half Carry
Bit Set
Branch if (H) = 1 − − − − − − REL 29 rr 3
BHI rel Branch if Higher Branch if (C) | (Z) = 0 − − − − − − REL 22 rr 3
BHS rel Branch if Higher or
Same (same as BCC)
Branch if (C) = 0 − − − − − − REL 24 rr 3
BIH rel Branch if IRQ Pin High Branch if IRQ pin = 1 − − − − − − REL 2F rr 3
Table continues on the next page...
Instruction Set Summary
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
268 Freescale Semiconductor, Inc.