Datasheet

Table 10-3. Instruction Set Summary (continued)
Source Form Operation Description
Effect on CCR
Address
Mode
Opcode
Operand
Bus Cycles
V H I N Z C
− − − − − ↕ DIR (b2) 04 dd rr 5
− − − − − ↕ DIR (b3) 06 dd rr 5
BRSET
n,opr8a,rel
Branch if Bit n in
Memory Set
Branch if (Mn) = 1
− − − − − ↕ DIR (b4) 08 dd rr 5
− − − − − ↕ DIR (b5) 0A dd rr 5
− − − − − ↕ DIR (b6) 0C dd rr 5
− − − − − ↕ DIR (b7) 0E dd rr 5
– – – – – – DIR (b0) 10 dd 5
– – – – – – DIR (b1) 12 dd 5
– – – – – – DIR (b2) 14 dd 5
– – – – – – DIR (b3) 16 dd 5
BSET n,opr8a
Set Bit n in Memory Mn ← 1
– – – – – – DIR (b4) 18 dd 5
– – – – – – DIR (b5) 1A dd 5
– – – – – – DIR (b6) 1C dd 5
– – – – – – DIR (b7) 1E dd 5
PC ← (PC) + 0x0002
push (PCL)
BSR rel
Branch to Subroutine SP ← (SP) – 0x0001
push (PCH)
– – – – – – REL AD rr 5
SP ← (SP) – 0x0001
PC ← (PC) + rel
CBEQ opr8a,rel Branch if (A) = (M) – – – – – – DIR 31 dd rr 5
CBEQA
#opr8i,rel
Branch if (A) = (M) – – – – – – IMM 41 ii rr 4
CBEQX
#opr8i,rel
Compare and Branch
if Equal
Branch if (X) = (M) – – – – – – IMM 51 ii rr 4
CBEQ oprx8,X
+,rel
Branch if (A) = (M) – – – – – – IX1+ 61 ff rr 5
CBEQ ,X+,rel Branch if (A) = (M) – – – – – – IX+ 71 rr 5
CBEQ
oprx8,SP,rel
Branch if (A) = (M) – – – – – – SP1 9E61 ff rr 6
CLC Clear Carry Bit C ← 0 – – – – – 0 INH 98 1
CLI Clear Interrupt Mask
Bit
I ← 0 – – 0 – – – INH 9A 1
CLR opr8a M ← 0x00 0 – – 0 1 – DIR 3F dd 5
CLRA A ← 0x00 0 – – 0 1 – INH 4F 1
CLRX X ← 0x00 0 – – 0 1 – INH 5F 1
CLRH
Clear
H ← 0x00 0 – – 0 1 – INH 8C 1
CLR oprx8,X M ← 0x00 0 – – 0 1 – IX1 6F ff 5
Table continues on the next page...
Instruction Set Summary
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
270 Freescale Semiconductor, Inc.