Datasheet

Table 10-3. Instruction Set Summary (continued)
Source Form Operation Description
Effect on CCR
Address
Mode
Opcode
Operand
Bus Cycles
V H I N Z C
CLR ,X M ← 0x00 0 – – 0 1 – IX 7F 4
CLR oprx8,SP M ← 0x00 0 – – 0 1 – SP1 9E6F ff 6
CMP #opr8i ↕ – – ↕ ↕ ↕ IMM A1 ii 2
CMP opr8a ↕ – – ↕ ↕ ↕ DIR B1 dd 3
CMP opr16a
↕ – – ↕ ↕ ↕ EXT C1 hh ll 4
CMP oprx16,X ↕ – – ↕ ↕ ↕ IX2 D1 ee ff 4
CMP oprx8,X
Compare Accumulator
with Memory
(A) – (M); (CCR
Updated But Operands
Not Changed)
↕ – – ↕ ↕ ↕ IX1 E1 ff 3
CMP ,X ↕ – – ↕ ↕ ↕ IX F1 3
CMP oprx16,SP ↕ – – ↕ ↕ ↕ SP2 9ED1 ee ff 5
CMP oprx8,SP ↕ – – ↕ ↕ ↕ SP1 9EE1 ff 4
COM opr8a M ← (M) = 0xFF – (M) 0 – – ↕ ↕ 1 DIR 33 dd 5
COMA A ← (A) = 0xFF – (A) 0 – – ↕ ↕ 1 INH 43 1
COMX
One’s Complement
X ← (X) = 0xFF – (X) 0 – – ↕ ↕ 1 INH 53 1
COM oprx8,X M ← (M) = 0xFF – (M) 0 – – ↕ ↕ 1 IX1 63 ff 5
COM ,X M ← (M) = 0xFF – (M) 0 – – ↕ ↕ 1 IX 73 4
COM oprx8,SP M ← (M) = 0xFF – (M) 0 – – ↕ ↕ 1 SP1 9E63 ff 6
CPHX opr16a ↕ – – ↕ ↕ ↕ EXT 3E hh ll 6
CPHX #opr16i ↕ – – ↕ ↕ ↕ IMM 65 jj kk 3
CPHX opr8a
Compare Index
Register (H:X) with
Memory
(H:X) – (M:M +
0x0001); (CCR
Updated But Operands
Not Changed)
↕ – – ↕ ↕ ↕ DIR 75 dd 5
CPHX oprx8,SP ↕ – – ↕ ↕ ↕ SP1 9EF3 ff 6
CPX #opr8i ↕ − − ↕ ↕ ↕ IMM A3 ii 2
CPX opr8a ↕ − − ↕ ↕ ↕ DIR B3 dd 3
CPX opr16a ↕ − − ↕ ↕ ↕ EXT C3 hh ll 4
CPX oprx16,X
Compare X (Index
Register Low) with
Memory
(X) – (M); (CCR
Updated But Operands
Not Changed)
↕ − − ↕ ↕ ↕ IX2 D3 ee ff 4
CPX oprx8,X ↕ − − ↕ ↕ ↕ IX1 E3 ff 3
CPX ,X ↕ − − ↕ ↕ ↕ IX F3 3
CPX oprx16,SP ↕ − − ↕ ↕ ↕ SP2 9ED3 ee ff 5
CPX oprx8,SP ↕ − − ↕ ↕ ↕ SP1 9EE3 ff 4
DAA Decimal Adjust
Accumulator After
ADD or ADC of BCD
Values
(A)
10
U − − ↕ ↕ ↕ INH 72 1
DBNZ opr8a,rel − − − − − − DIR 3B dd rr 7
Table continues on the next page...
Chapter 10 Central processor unit
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 271