Datasheet

Table 10-3. Instruction Set Summary (continued)
Source Form Operation Description
Effect on CCR
Address
Mode
Opcode
Operand
Bus Cycles
V H I N Z C
PSHX Push X (Index
Register Low) onto
Stack
Push (X); SP ← (SP) –
0x0001
− − − − − − INH 89 2
PULA Pull Accumulator from
Stack
SP ← (SP + 0x0001);
Pull (A)
− − − − − − INH 86 3
PULH Pull H (Index Register
High) from Stack
SP ← (SP + 0x0001);
Pull (H)
− − − − − − INH 8A 3
PULX Pull X (Index Register
Low) from Stack
SP ← (SP + 0x0001);
Pull (X)
− − − − − − INH 88 3
ROL opr8a ↕ − − ↕ ↕ ↕ DIR 39 dd 5
ROLA ↕ − − ↕ ↕ ↕ INH 49 1
ROLX ↕ − − ↕ ↕ ↕ INH 59 1
ROL oprx8,X
Rotate Left through
Carry
C ← MSB, LSB ← C
↕ − − ↕ ↕ ↕ IX1 69 ff 5
ROL ,X ↕ − − ↕ ↕ ↕ IX 79 4
ROL oprx8,SP ↕ − − ↕ ↕ ↕ SP1 9E69 ff 6
ROR opr8a ↕ − − ↕ ↕ ↕ DIR 36 dd 5
RORA ↕ − − ↕ ↕ ↕ INH 46 1
RORX ↕ − − ↕ ↕ ↕ INH 56 1
ROR oprx8,X
Rotate Right through
Carry
LSB → C, C → MSB
↕ − − ↕ ↕ ↕ IX1 66 ff 5
ROR ,X ↕ − − ↕ ↕ ↕ IX 76 4
ROR oprx8,SP ↕ − − ↕ ↕ ↕ SP1 9E66 ff 6
RSP Reset Stack Pointer SP ← 0xFF (High Byte
Not Affected)
− − − − − − INH 9C 1
SP ← (SP) + 0x0001,
Pull (CCR)
SP ← (SP) + 0x0001,
Pull (A)
RTI
Return from Interrupt SP ← (SP) + 0x0001,
Pull (X)
↕ ↕ ↕ ↕ ↕ ↕ INH 80 9
SP ← (SP) + 0x0001,
Pull (PCH)
SP ← (SP) + 0x0001,
Pull (PCL)
SP ← SP + 0x0001, Pull
(PCH)
RTS
Return from
Subroutine
− − − − − − INH 81 6
SP ← SP + 0x0001, Pull
(PCL)
SBC #opr8i ↕ − − ↕ ↕ ↕ IMM A2 ii 2
Table continues on the next page...
Chapter 10 Central processor unit
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 275