Datasheet

11.4.1 KBI Status and Control Register (KBIx_SC)
KBI_SC contains the status flag and control bits, which are used to configure the KBI.
Address: Base address + 0h offset
Bit 7 6 5 4 3 2 1 0
Read 0 KBF
KBIE KBMOD
Write KBACK
Reset
0 0 0 0 0 0 0 0
KBIx_SC field descriptions
Field Description
7–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
KBF
KBI Interrupt Flag
KBF indicates when a KBI interrupt request is detected. Writes have no effect on KBF.
0 KBI interrupt request not detected.
1 KBI interrupt request detected.
2
KBACK
KBI Acknowledge
Writing a 1 to KBACK is part of the flag clearing mechanism.
1
KBIE
KBI Interrupt Enable
KBIE determines whether a KBI interrupt is enabled or not.
0 KBI interrupt not enabled.
1 KBI interrupt enabled.
0
KBMOD
KBI Detection Mode
KBMOD (along with the KBEDG bits) controls the detection mode of the KBI interrupt pins.
0 Keyboard detects edges only.
1 Keyboard detects both edges and levels.
11.4.2 KBIx Pin Enable Register (KBIx_PE)
KBIx_PE contains the pin enable control bits.
Address: Base address + 3040h offset
Bit 7 6 5 4 3 2 1 0
Read
KBIPE
Write
Reset
0 0 0 0 0 0 0 0
Memory Map and Registers
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
282 Freescale Semiconductor, Inc.