Datasheet

11.5.1 Edge-Only Sensitivity
Synchronous logic is used to detect edges. A falling edge is detected when an enabled
keyboard interrupt (KBIPEn=1) input signal is seen as a logic 1 (the deasserted level)
during one bus cycle and then a logic 0 (the asserted level) during the next cycle. A rising
edge is detected when the input signal is seen as a logic 0 (the deasserted level) during
one bus cycle and then a logic 1 (the asserted level) during the next cycle.
Before the first edge is detected, all enabled keyboard interrupt input signals must be at
the deasserted logic levels. After any edge is detected, all enabled keyboard interrupt
input signals must return to the deasserted level before any new edge can be detected.
A valid edge on an enabled KBI pin will set KBF in KBIxSC. If KBIE in KBIxSC is set,
an interrupt request will be presented to the MPU. Clearing of KBF is accomplished by
writing a 1 to KBACK in KBIxSC.
11.5.2 Edge and Level Sensitivity
A valid edge or level on an enabled KBI pin will set KBF in KBIxSC. If KBIE in
KBIxSC is set, an interrupt request will be presented to the MCU. Clearing of KBF is
accomplished by writing a 1 to KBACK in KBIxSC, provided all enabled keyboard
inputs are at their deasserted levels. KBF will remain set if any enabled KBI pin is
asserted while attempting to clear KBF by writing a 1 to KBACK.
11.5.3 KBI Pullup Resistor
Each KBI pin, if enabled by KBIxPE, can be configured via the associated I/O port pull
enable register (see I/O Port chapter) to use:
• an internal pullup resistor, or
• no resistor
If an internal pullup resistor is enabled for an enabled KBI pin, the associated I/O port
pull select register (see I/O Port chapter) can be used to select an internal pullup resistor.
Functional Description
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
284 Freescale Semiconductor, Inc.