Datasheet

CLKS[1:0]
FTMEN
CAPTEST
CPWMS
FAULTM[1:0]
FFVAL[3:0]
FAULTIE
FAULTnEN*
FFLTRnEN*
fault input n*
fixed frequency clock
external clock
system clock
no clock selected
(FTM counter disable)
synchronizer
divided
by 2
PS[2:0]
3(
1, 2, 4, 8, 16, 32, 64 or 128)
Prescaler
initialization
trigger
timer overflow
interrupt
INITTRIGEN
TOIE
TOF
CNTINH:L
MODH:L
FAULTIN
FAULTF
FAULTFn*
FTM counter
(16-bit counter)
Fault control
*where n = 3, 2, 1, 0
fault interrupt
fault condition
channel 0
input
Input capture
mode logic
DECAPEN
COMBINE
CPWMS
MS0B:MS0A
ELS0B:ELS0A
CH0IE
CH0F
CH0TRIG
channel 0
interrupt
channel 0
match trigger
channel 0
output
channel 1
output
channel 1
match trigger
CH1TRIG
C0VH:L
C1VH:L
channel 1
input
Initialization
Output modes
logic
Deadtime
insertion
Fault
control
Polarity
control
Output
mask
COMP
MS1B:MS1A
ELS1B:ELS1A
Input capture
mode logic
DECAPEN
COMBINE
CPWMS
CH1F
CH1IE
channel 1
interrupt
channel 6
interrupt
DTEN
DTPS[1:0]
DTVAL[5:0]
INT
CH0OI
CH1OI
FAULTM[1:0]
FAULTEN
POL0
POL1
SYNCHOM
CH0OM
CH1OM
SYNCHOM
CH6OM
CH7OM
DTEN
DTPS[1:0]
DTVAL[5:0]
INT
CH6OI
CH7OI
FAULTM[1:0]
FAULTEN
POL6
POL7
channel 6
output
channel 7
output
Initialization
Output modes
logic
Deadtime
insertion
Fault
control
Polarity
control
Output
mask
channel 7
interrupt
CH6IE
CH6F
DECAPEN
COMBINE
CPWMS
MS6B:MS6A
ELS6B:ELS6A
channel 6
input
channel 7
input
Input capture
mode logic
C6VH:L
C7VH:L
Input capture
mode logic
DECAPEN
COMBINE
CPWMS
COMP
MS7B:MS7A
ELS7B:ELS7A
CH7F
CH7IE
Dual edge
capture
mode logic
Dual edge
capture
mode logic
Figure 12-1. FTM block diagram
Chapter 12 FlexTimer Module (FTM)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 291