Datasheet

12.3 Memory map and register definition
This section provides a detailed description of all FTM registers.
12.3.1 Module memory map
This section presents a high-level summary of the FTM registers and how they are
mapped.
The FTM memory map can be split into two sets of registers. The first set has the original
TPM registers.
Starting with Counter Initial Value High (CNTINH), the second set has the FTM specific
registers. Any second set registers, or bits within these registers, that are used by an
unavailable function in the FTM configuration remain in the memory map and in the
reset value even though they have no active function.
Note
Do not write to the FTM specific registers (second set registers)
when FTMEN = 0.
12.3.2 Register descriptions
This section consists of register descriptions in address order.
FTM memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
20 Status and Control (FTM0_SC) 8 R/W 00h 12.3.3/297
21 Counter High (FTM0_CNTH) 8 R/W 00h 12.3.4/298
22 Counter Low (FTM0_CNTL) 8 R/W 00h 12.3.5/299
23 Modulo High (FTM0_MODH) 8 R/W 00h 12.3.6/299
24 Modulo Low (FTM0_MODL) 8 R/W 00h 12.3.7/300
25 Channel Status and Control (FTM0_C0SC) 8 R/W 00h 12.3.8/300
26 Channel Value High (FTM0_C0VH) 8 R/W 00h 12.3.9/303
27 Channel Value Low (FTM0_C0VL) 8 R/W 00h 12.3.10/304
28 Channel Status and Control (FTM0_C1SC) 8 R/W 00h 12.3.8/300
29 Channel Value High (FTM0_C1VH) 8 R/W 00h 12.3.9/303
Table continues on the next page...
Chapter 12 FlexTimer Module (FTM)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 293