Datasheet

FTM memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
2A Channel Value Low (FTM0_C1VL) 8 R/W 00h 12.3.10/304
2B Channel Status and Control (FTM0_C2SC) 8 R/W 00h 12.3.8/300
2C Channel Value High (FTM0_C2VH) 8 R/W 00h 12.3.9/303
2D Channel Value Low (FTM0_C2VL) 8 R/W 00h 12.3.10/304
2E Channel Status and Control (FTM0_C3SC) 8 R/W 00h 12.3.8/300
2F Channel Value High (FTM0_C3VH) 8 R/W 00h 12.3.9/303
30 Channel Value Low (FTM0_C3VL) 8 R/W 00h 12.3.10/304
31 Channel Status and Control (FTM0_C4SC) 8 R/W 00h 12.3.8/300
32 Channel Value High (FTM0_C4VH) 8 R/W 00h 12.3.9/303
33 Channel Value Low (FTM0_C4VL) 8 R/W 00h 12.3.10/304
34 Channel Status and Control (FTM0_C5SC) 8 R/W 00h 12.3.8/300
35 Channel Value High (FTM0_C5VH) 8 R/W 00h 12.3.9/303
36 Channel Value Low (FTM0_C5VL) 8 R/W 00h 12.3.10/304
37 Counter Initial Value High (FTM0_CNTINH) 8 R/W 00h 12.3.11/304
38 Counter Initial Value Low (FTM0_CNTINL) 8 R/W 00h 12.3.12/305
39 Capture and Compare Status (FTM0_STATUS) 8 R/W 00h 12.3.13/305
3A Features Mode Selection (FTM0_MODE) 8 R/W 04h 12.3.14/307
3B Synchronization (FTM0_SYNC) 8 R/W 00h 12.3.15/309
3C Initial State for Channel Output (FTM0_OUTINIT) 8 R/W 00h 12.3.16/311
3D Output Mask (FTM0_OUTMASK) 8 R/W 00h 12.3.17/312
3E Function for Linked Channels (FTM0_COMBINE0) 8 R/W 00h 12.3.18/313
3F Function for Linked Channels (FTM0_COMBINE1) 8 R/W 00h 12.3.18/313
40 Function for Linked Channels (FTM0_COMBINE2) 8 R/W 00h 12.3.18/313
42 Deadtime Insertion Control (FTM0_DEADTIME) 8 R/W 00h 12.3.19/315
43 External Trigger (FTM0_EXTTRIG) 8 R/W 00h 12.3.20/316
44 Channels Polarity (FTM0_POL) 8 R/W 00h 12.3.21/317
45 Fault Mode Status (FTM0_FMS) 8 R/W 00h 12.3.22/319
46 Input Capture Filter Control (FTM0_FILTER0) 8 R/W 00h 12.3.23/321
47 Input Capture Filter Control (FTM0_FILTER1) 8 R/W 00h 12.3.23/321
48 Fault Input Filter Control (FTM0_FLTFILTER) 8 R/W 00h 12.3.24/322
49 Fault Input Control (FTM0_FLTCTRL) 8 R/W 00h 12.3.25/322
30 Status and Control (FTM1_SC) 8 R/W 00h 12.3.3/297
31 Counter High (FTM1_CNTH) 8 R/W 00h 12.3.4/298
32 Counter Low (FTM1_CNTL) 8 R/W 00h 12.3.5/299
33 Modulo High (FTM1_MODH) 8 R/W 00h 12.3.6/299
34 Modulo Low (FTM1_MODL) 8 R/W 00h 12.3.7/300
35 Channel Status and Control (FTM1_C0SC) 8 R/W 00h 12.3.8/300
36 Channel Value High (FTM1_C0VH) 8 R/W 00h 12.3.9/303
Table continues on the next page...
Memory map and register definition
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
294 Freescale Semiconductor, Inc.