Datasheet

FTMx_SC field descriptions (continued)
Field Description
2–0
PS
Prescale Factor Selection
Selects one of 8 division factors for the clock source selected by CLKS. The new prescaler factor affects
the clock source on the next system clock cycle after the new value is updated into the register bits.
PS is write protected. It can be written only when MODE[WPDIS] = 1.
000 Divide by 1
001 Divide by 2
010 Divide by 4
011 Divide by 8
100 Divide by 16
101 Divide by 32
110 Divide by 64
111 Divide by 128
12.3.4 Counter High (FTMx_CNTH)
The Counter registers contain the high and low bytes of the counter value. Reading either
byte latches the contents of both bytes into a buffer where they remain latched until the
other half is read. This allows coherent 16-bit reads in either big-endian or little-endian
order which makes this more friendly to various compiler implementations. The
coherency mechanism is automatically restarted by an MCU reset or any write to the
Status and Control register.
Writing any value to COUNT_H or COUNT_L updates the FTM counter with its initial
16-bit value (contained in the Counter Initial Value registers) and resets the read
coherency mechanism, regardless of the data involved in the write.
When BDM is active, the FTM counter is frozen (this is the value that you may read); the
read coherency mechanism is frozen such that the buffer latches remain in the state they
were in when the BDM became active, even if one or both counter bytes are read while
BDM is active. This assures that if you were in the middle of reading a 16-bit register
when BDM became active, it reads the appropriate value from the other half of the 16-bit
value after returning to normal execution.
Address: Base address + 1h offset
Bit 7 6 5 4 3 2 1 0
Read
COUNT_H
Write
Reset
0 0 0 0 0 0 0 0
Memory map and register definition
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
298 Freescale Semiconductor, Inc.