Datasheet

FTMx_CNTH field descriptions
Field Description
7–0
COUNT_H
Counter value high byte
12.3.5 Counter Low (FTMx_CNTL)
See the description for the Counter High register.
Address: Base address + 2h offset
Bit 7 6 5 4 3 2 1 0
Read
COUNT_L
Write
Reset
0 0 0 0 0 0 0 0
FTMx_CNTL field descriptions
Field Description
7–0
COUNT_L
Counter value low byte
12.3.6 Modulo High (FTMx_MODH)
The Modulo registers contain the high and low bytes of the modulo value for the FTM
counter. After the FTM counter reaches the modulo value, the overflow flag (TOF)
becomes set at the next clock, and the next value of FTM counter depends on the selected
counting method (Counter).
Writing to either byte latches the value into a buffer. The register is updated with the
value of their write buffer according to Update of the registers with write buffers.
If MODE[FTMEN] = 0, this write coherency mechanism may be manually reset by
writing to the SC register whether BDM is active or not.
When BDM is active, this write coherency mechanism is frozen such that the buffer
latches remain in the state they were in when the BDM became active, even if one or both
bytes of the modulo register are written while BDM is active. Any write to the modulo
register bypasses the buffer latches and directly writes to the modulo register while BDM
is active.
Chapter 12 FlexTimer Module (FTM)
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
Freescale Semiconductor, Inc. 299