Datasheet

It is recommended to initialize the FTM counter, by writing to CNTH or CNTL, before
writing to the FTM modulo register to avoid confusion about when the first counter
overflow will occur.
Address: Base address + 3h offset
Bit 7 6 5 4 3 2 1 0
Read
MOD_H
Write
Reset
0 0 0 0 0 0 0 0
FTMx_MODH field descriptions
Field Description
7–0
MOD_H
High byte of the modulo value
12.3.7 Modulo Low (FTMx_MODL)
See the description for the Modulo High register.
Address: Base address + 4h offset
Bit 7 6 5 4 3 2 1 0
Read
MOD_L
Write
Reset
0 0 0 0 0 0 0 0
FTMx_MODL field descriptions
Field Description
7–0
MOD_L
Low byte of the modulo value
12.3.8 Channel Status and Control (FTMx_CnSC)
CnSC contains the channel-interrupt-status flag and control bits used to configure the
interrupt enable, channel configuration, and pin function.
Table 12-70. Mode, edge, and level selection
DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration
X X X XX 00 None Pin not used for
FTM
Table continues on the next page...
Memory map and register definition
MC9S08PA60 Reference Manual, Rev. 1, 9/2012
300 Freescale Semiconductor, Inc.